VS6663CD datasheet(40/64 Pages) STMICROELECTRONICS

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Video timing

VS6663CD

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Doc ID027033 Rev 2

Figure 14. Analog crop

The host must ensure the following rules are kept:

•

the end address must be greater than the start address

•

the x and y start addresses are restricted to even numbers only, and the x and y end

addresses are restricted to odd numbers only, to ensure that there is always a even

number of pixels read-out

6.1.2

Binning

The VS6663CD also has a binning mode that offers a reduced size full field of view image.

The binning mode averages row and column pixel data.

The binning mode results in a reduced number of lines and so can be used to give a higher

image frame rate. Compared to subsampling, binning makes use of the light gathered from

the whole pixel array and it results in higher image quality.

The binning mode will scale by 2x2 in the X and Y direction. Entering and exiting binning

mode may or may not be performed when the sensor is in software standby.

Table 23 summarizes the register setting for enabling binning mode. (The x/y_odd_inc

registers are automatically set and do not require to be set by the user.)

y_addr_max = 975

x_addr_max = 1295

y_addr_min = 0

x_addr_min = 0

x_addr_max, y_addr_max

x_addr_end, y_addr_end

Addressed

pixel array region

x_addr_start, y_addr_start

x_addr_min, y_addr_min

Table 23. Binning register settings

Address

Normal

Binning 2x2

binning_mode

0x0900

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