DMA Control Bus Arbitration

TLF8582 – 80

Symbol

Parameter

Min

Max

Units

brqhl

Bus Clock to Bus Request High for Local DMA

43

ns

brqhr

Bus Clock to Bus Request High for Remote DMA

38

ns

brql

Bus Request Low from Bus Clock

55

ns

backs

Acknowledge Setup to Bus Clock

2ns

(Note 1)

bccte

Bus Clock to Control Enable

60

ns

bcctr

Bus Clock to Control Release

70

ns

(Notes 2 3)

Note 1

BACK must be setup before T1 after BREQ is asserted Missed setup will slip the beginning of the DMA by four bus clocks The Bus Latency will influence

the allowable FIFO threshold and transfer mode (emptyfill vs exact burst transfer)

Note 2

During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed

Note 3

These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention

43