DP8390D datasheet(13/56 Pages) NSC

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90 Remote DMA (Continued)

REMOTE WRITE

A Remote Write transfer is used to move a block of data

from the host into local buffer memory The Remote DMA

will read data from the IO port and sequentially write it to

local buffer memory beginning at the Remote Start Address

The DMA Address will be incremented and the Byte Coun-

ter will be decremented after each transfer The DMA is

terminated when the Remote Byte Count Register reaches

a count of zero

REMOTE READ

A Remote Read transfer is used to move a block of data

from local buffer memory to the host The Remote DMA will

sequentially read data from the local buffer memory begin-

ning at the Remote Start Address and write data to the IO

port The DMA Address will be incremented and the Byte

Counter will be decremented after each transfer The DMA

is terminated when the Remote Byte Count Register reach-

es zero

REMOTE DMA WRITE

Setting PRQ Using the Remote Read

Under certain conditions the NIC’s bus state machine may

issue MWR and PRD before PRQ for the first DMA trans-

fer of a Remote Write Command If this occurs this could

cause data corruption or cause the remote DMA count to

be different from the main CPU count causing the system to

‘‘lock up’’

To prevent this condition when implementing a Remote

DMA Write the Remote DMA Write command should first

be preceded by a Remote DMA Read command to insure

that the PRQ signal is asserted before the NIC starts its port

read cycle The reason for this is that the state machine that

asserts PRQ runs independently of the state machine that

controls the DMA signals The DMA machine assumes that

PRQ is asserted but actually may not be To remedy this

situation a single Remote Read cycle should be inserted

before the actual DMA Write Command is given This will

ensure that PRQ is asserted when the Remote DMA Write is

subsequently executed This single Remote Read cycle is

called a ‘‘dummy Remote Read’’ In order for the dummy

Remote Read cycle to operate correctly the Start Address

should be programmed to a known safe location in the buff-

er memory space and the Remote Byte Count should be

progammed to a value greater than 1 This will ensure that

the master read cycle is performed safely eliminating the

possiblity of data corruption

Remote Write with High Speed Buses

When implementing the Remote DMA Write solution in pre-

vious section with high speed buses and CPU’s timing

problems may cause the system to hang Therefore addi-

tional considerations are required

The problem occurs when the system can execute the dum-

my Remote Read and then start the Remote Write before

the NIC has had a chance to execute the Remote Read If

this happens the PRQ signal will not get set and the Re-

mote Byte Count and Remote Start Address for the Remote

Write operation could be corrupted This is shown by the

hatched waveforms in the timing diagram below The execu-

tion of the Remote Read can be delayed by the local DMA

operations (particularly during end-of-packet processing)

To ensure the dummy Remote Read does execute a delay

must be inserted between writing the Remote Read Com-

mand and starting to write the Remote Write Start Address

(This time is designated in figure below by the delay arrows)

The recommended method to avoid this problem is after

the Remote Read command is given to poll both bytes of

the Current Remote DMA Address Registers When the ad-

dress has incremented PRQ has been set Software should

recognize this and then start the Remote Write

An additional caution for high speed systems is that the

polling must follow guidelines specified at the end of Sec-

tion 13 That is there must be at least 4 bus clocks between

chip selects (For example when BSCK e 20 MHz then

this time should be 200 ns)

The general flow for executing a Remote Write is

1 Set Remote Byte Count to a value l1 and Remote Start

Address to unused RAM (one location before the transmit

start address is usually a safe location)

TLF8582 – 96

Timing Diagram for Dummy Remote Read

Note

The dashed lines indicate incorrect timing

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