103 Register Descriptions

(Continued)

INTERRUPT MASK REGISTER (IMR)

0FH (WRITE)

The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status

Register (ISR) If an interrupt mask bit is set an interrupt will be issued whenever the corresponding bit in the ISR is set If any bit

in the IMR is set low an interrupt will not occur when the bit in the ISR is set The IMR powers up all zeroes

765

4

3210

RDCE CNTE OVWE TXEE RXEE PTXE PRXE

Bit

Symbol

Description

D0

PRXE

PACKET RECEIVED INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when packet received

D1

PTXE

PACKET TRANSMITTED INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when packet is transmitted

D2

RXEE

RECEIVE ERROR INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when packet received with error

D3

TXEE

TRANSMIT ERROR INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when packet transmission results in error

D4

OVWE

OVERWRITE WARNING INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when Buffer Management Logic lacks sufficient buffers to

store incoming packet

D5

CNTE

COUNTER OVERFLOW INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when MSB of one or more of the Network Statistics

counters has been set

D6

RDCE

DMA COMPLETE INTERRUPT ENABLE

0 Interrupt Disabled

1 Enables Interrupt when Remote DMA transfer has been completed

D7

reserved

reserved

21