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DP8390D 数据表(PDF) 51 Page - National Semiconductor (TI) |
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DP8390D 数据表(HTML) 51 Page - National Semiconductor (TI) |
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51 / 56 page ![]() 150 Switching Characteristics (Continued) Remote DMA (Write Cycle) Recovery Time TLF8582 – 87 Symbol Parameter Min Max Units bprqh Bus Clock to Port Request High 40 ns (Note 1) wprql WACK to Port Request Low 45 ns wackw WACK Pulse Width 20 ns bprdl Bus Clock to Port Read Low 40 ns (Note 2) bprdh Bus Clock to Port Read High 40 ns wprq Remote Write Port Request to Port Request Time 12 BUSCK (Notes 345) Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA cycles Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BUSCK and whether a local DMA is pending Note 3 Assuming wackw k 1 BUSCK and no local DMA interleave no CS immediate BACK and WACK goes high before T4 Note 4 WACK must be high for a minimum of 7 BUSCK Note 5 This is not a measured value but guaranteed by design 51 |
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