DP8390D datasheet(22/56 Pages) NSC

22 / 56 page

100 Internal Registers (Continued)

103 Register Descriptions

(Continued)

DATA CONFIGURATION REGISTER (DCR)

0EH (WRITE)

This Register is used to program the NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and

establish FIFO threshholds The DCR must be initialized prior to loading the Remote Byte Count Registers LAS is set on

power up

76543210

FT1

FT0

ARM

LAS

BOS

WTS

Bit

Symbol

Description

WTS

WORD TRANSFER SELECT

0 Selects byte-wide DMA transfers

1 Selects word-wide DMA transfers

WTS establishes byte or word transfers

for both Remote and Local DMA transfers

Note

When word-wide mode is selected up to 32k words are addressable A0 remains low

BOS

BYTE ORDER SELECT

0 MS byte placed on AD15 – AD8 and LS byte on AD7 – AD0 (32000 8086)

1 MS byte placed on AD7 – AD0 and LS byte on AD15 – AD8 (68000)

Ignored when WTS is low

LAS

LONG ADDRESS SELECT

0 Dual 16-bit DMA mode

1 Single 32-bit DMA mode

When LAS is high the contents of the Remote DMA registers RSAR01 are issued as A16 – A31

Power up high

LOOPBACK SELECT

0 Loopback mode selected Bits D1 D2 of the TCR must also be programmed for Loopback

operation

1 Normal Operation

AUTO-INITIALIZE REMOTE

0 Send Command not executed all packets removed from Buffer Ring under program control

1 Send Command executed Remote DMA auto-initialized to remove packets from Buffer Ring

Note

Send Command cannot be used with 68000 type processors

D5 D6

FT0 FT1

FIFO THRESHHOLD SELECT

Encoded FIFO threshhold Establishes point at which bus is

requested when filling or emptying the FIFO During reception the FIFO threshold indicates the

number of bytes (or words) the FIFO has filled serially from the network before bus request

(BREQ) is asserted

Note

FIFO threshold setting determines the DMA burst length

RECEIVE THRESHOLDS

FT1

FT0

Word Wide

Byte Wide

1 Word

2 Bytes

2 Words

4 Bytes

4 Words

8 Bytes

6 Words

12 Bytes

During transmission the FIFO threshold indicates the numer of bytes (or words) the FIFO has

filled from the Local DMA before BREQ is asserted Thus the transmission threshold is 16 bytes

less the receive threshold

DP8390D 数据表(PDF) 22 Page - National Semiconductor (TI)

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DP8390D 数据表(PDF) 22 Page - National Semiconductor (TI)

DP8390D 数据表(HTML) 22 Page - National Semiconductor (TI)

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