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DP8390D 数据表(PDF) 53 Page - National Semiconductor (TI) |
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DP8390D 数据表(HTML) 53 Page - National Semiconductor (TI) |
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53 / 56 page ![]() 150 Switching Characteristics (Continued) Serial TimingTransmit (Beginning of Frame) TLF8582 – 90 Symbol Parameter Min Max Units txch Transmit Clock High Time 36 ns txcl Transmit Clock Low Time 36 ns txcyc Transmit Clock Cycle Time 80 120 ns txcenh Transmit Clock to Transmit Enable High 48 ns (Note 1) txcsdv Transmit Clock to Serial Data Valid 67 ns txcsdh Serial Data Hold Time from 10 ns Transmit Clock High Note 1 The NIC issues TXEN coincident with the first bit of preamble The first bit of preamble is always a 1 Serial TimingTransmit (End of Frame CD Heartbeat) TLF8582 – 91 Symbol Parameter Min Max Units tcdl Transmit Clock to Data Low 55 ns tcenl Transmit Clock to TXEN Low 55 ns tdcdh TXEN Low to Start of Collision 064 txcyc Detect Heartbeat (Note 1) cycles cdhw Collision Detect Width 2 txcyc cycles Note 1 If COL is not seen during the first 64 TX clock cycles following de-assertion of TXEN the CDH bit in the TSR is set 53 |
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