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DP8390D 数据表(PDF) 49 Page - National Semiconductor (TI) |
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DP8390D 数据表(HTML) 49 Page - National Semiconductor (TI) |
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49 / 56 page ![]() 150 Switching Characteristics (Continued) Remote DMA (Read Send Command) Recovery Time TLF8582 – 85 Symbol Parameter Min Max Units bpwrl Bus Clock to Port Write Low 43 ns bpwrh Bus Clock to Port Write High 40 ns prqh Port Write High to Port 30 ns Request High (Note 1) prql Port Request Low from 45 ns Read Acknowledge High rakw Remote Acknowledge 20 ns Read Strobe Pulse Width rhpwh Read Acknowledge High to Next Port Write Cycle 11 BUSCK (Notes 234) Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending Note 2 This is not a measured value but guaranteed by design Note 3 RACK must be high for a minimum of 7 BUSCK Note 4 Assumes no local DMA interleave no CS and immediate BACK 49 |
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