DMA Address Generation

TLF8582 – 81

Symbol

Parameter

Min

Max

Units

bcyc

Bus Clock Cycle Time

50

1000

ns

(Note 2)

bch

Bus Clock High Time

225

ns

bcl

Bus Clock Low Time

225

ns

bcash

Bus Clock to Address Strobe High

34

ns

bcasl

Bus Clock to Address Strobe Low

44

ns

aswo

Address Strobe Width Out

bch

ns

bcadv

Bus Clock to Address Valid

45

ns

bcadz

Bus Clock to Address TRI-STATE

15

55

ns

(Note 3)

ads

Address Setup to ADS01 Low

ns

adh

Address Hold from ADS01 Low

Note 1

Cycles T1’ T2’ T3’ T4’ are only issued for the first transfer in a burst when 32-bit mode has been selected

Note 2

The rate of bus clock must be high enough to support transfers tofrom the FIFO at a rate greater than the serial network transfers fromto the FIFO

Note 3

These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention

44