Serial TimingReceive (Beginning of Frame)

TLF8582 – 88

Symbol

Parameter

Min

Max

Units

rch

Receive Clock High Time

40

ns

rcl

Receive Clock Low Time

40

ns

rcyc

Receive Clock Cycle Time

80

120

ns

rds

Receive Data Setup Time to

20

ns

Receive Clock High (Note 1)

rdh

Receive Data Hold Time from

17

ns

Receive Clock High

pts

First Preamble Bit to Synch

8

rcyc

(Note 2)

cycles

Note 1

All bits entering NIC must be properly decoded if the PLL is still locking the clock to the NIC should be disabled or CRS delayed Any two sequential 1 data

bits will be interpreted as Synch

Note 2

This is a minimum requirement which allows reception of a packet

Serial TimingReceive (End of Frame)

TLF8582 – 89

Symbol

Parameter

Min

Max

Units

rxrck

Minimum Number of Receive Clocks

5

rcyc

after CRS Low (Note 1)

cycles

tdrb

Maximum of Allowed Dribble BitsClocks

3

rcyc

(Note 2)

cycles

tifg

Receive Recovery Time

40

rcyc

(Notes 45)

cycles

tcrsl

Receive Clock to Carrier Sense Low

01

rcyc

(Note 3)

cycles

Note 1

The NIC requires a minimum number of receive clocks following the de-assertion of carrier sense (CRS) These additional clocks are provided by the

DP8391 SNI If other decoderPLLs are being used additional clocks should be provided Short clocks or glitches are not allowed

Note 2

Up to 5 bits of dribble bits can be tolerated without resulting in a receive error

Note 3

Guarantees to only load bit N additional bits up to tdrb can be tolerated

Note 4

This is the time required for the receive state machine to complete end of receive processing This parameter is not measured but is guaranteed by design

This is not a measured parameter but is a design requirement

Note 5

CRS must remain de-asserted for a minimum of 2 RXC cycles to be recognized as end of carrier

52