ADE7758 datasheet(39/68 Pages) AD

39 / 68 page

ADE7758

Rev. A | Page 39 of 68

For a pure sinusoidal system, the two approaches should yield

the same result. The apparent energy calculation in the ADE7758

uses the arithmetical approach. However, the line cycle energy

accumulation mode in the ADE7758 enables energy accumula-

tion between active and reactive energies over a synchronous

period of time, thus the vectorial method can be easily

implemented in the external MCU (see the Line Cycle Active

Energy Accumulation Mode section).

Note that apparent power is always positive regardless of the

direction of the active or reactive energy flows. The rms value of

the current and voltage in each phase is multiplied to produce

the apparent power of the corresponding phase. The output

from the multiplier is then low-pass filtered to obtain the

average apparent power. The frequency response of the LPF in

the apparent power signal path is identical to that of the LPF2

used in the average active power calculation (see Figure 65).

Apparent Power Gain Calibration

Note that the average active power result from the LPF output

in each phase can be scaled by ±50% by writing to the phase’s

VAGAIN register (AVAG, BVAG, or CVAG). The VAGAIN

registers are twos complement, signed registers and have a

resolution of 0.024%/LSB. The function of the VAGAIN

registers is expressed below mathematically.

Power

Apparent

Average

⎟

⎠

⎞

⎜

⎝

⎛ +

VAGAIN

Output

LPF

The output is scaled by –50% when the VAR gain registers

contents are set to 0x800 and the output is increased by +50%

by writing 0x7FF to the watt gain register. This register can be

used to calibrate the apparent power (or energy) calculation in

the ADE7758 for each phase.

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation

value (see the Current RMS Calculation and Voltage Channel

RMS Calculation sections). The voltage and current rms values

are then multiplied together in the apparent power signal

processing. As no additional offsets are created in the

multiplication of the rms values, there is no specific offset

compensation in the apparent power signal processing. The

offset compensation of the apparent power measurement in

each phase should be done by calibrating each individual rms

measurement (see the Calibration section).

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

Apparent Energy = ∫ S(t) dt

(24)

Similar to active and reactive energy, the ADE7758 achieves the

integration of the apparent power signal by continuously

accumulating the apparent power signal in the internal 40-bit,

unsigned accumulation registers. The VA-hr registers (AVAHR,

BVAHR, and CVAHR) represent the upper 16 bits of these

internal registers. This discrete time accumulation or summation

is equivalent to integration in continuous time. Equation 25

below expresses the relationship

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

Energy

Apparent

(25)

where n is the discrete time sample number and T is the sample

period.

Figure 75 shows the signal path of the apparent energy accumu-

lation. The apparent power signal is continuously added to the

internal apparent energy register. The average apparent power is

divided by the content of the VA divider register before they are

added to the corresponding VA-hr accumulation registers. When

the value in the VADIV[7:0] register is 0 or 1, apparent power is

accumulated without any division. VADIV is an 8-bit unsigned

VA-hr accumulation registers overflow.

Similar to active or reactive power accumulation, the fastest

integration time occurs when the VAGAIN registers are set to

maximum full scale, i.e., 0x7FF. When overflow occurs, the

VA-hr accumulation registers contents can roll over to 0 and

continue increasing in value. By setting the VAEHF bit (Bit 2) of

the mask register, the ADE7758 can be configured to issue an

interrupt (IRQ) when the MSB of any one of the three VA-hr

accumulation registers has changed, indicating that the

accumulation register is half full.

Setting the RSTREAD bit (Bit 6) of the LCYMODE register

enables a read-with-reset for the VA-hr accumulation registers,

i.e., the registers are reset to 0 after a read operation.

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation

signals on the analog inputs and the VAGAIN registers set to

0x000, the average word value from each LPF2 is 0xB9954. The

maximum value that can be stored in the apparent energy

word value is first added to the internal register, which can store

241 − 1 or 0x1FF, FFFF, FFFF before it overflows, the integration

time under these conditions with VADIV = 0 is calculated as

second

1.157

μs

0.4

0xB9954

FFFF

FFFF,

0x1FF,

Time

When VADIV is set to a value different from 0, the time before

overflow is scaled accordingly as shown in Equation 26.

(

) VADIV

VADIV

Time

(26)

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