ADE7758 datasheet(43/68 Pages) AD

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ADE7758

Rev. A | Page 43 of 68

START

STEP 1

STEP 1A

ENABLE CF AND

VARCF PULSE

OUTPUTS

STEP 2

SET GAIN REGISTERS: XWG,

XVAG, XVARG TO LOGIC 0

SELECT VA FOR

VARCF OUTPUT

CFNUM/VARCFNUM

SET TO CALCULATE

VALUES?

YES

ALL

PHASES VA

AND WATT

GAIN CAL?

YES

STEP 3

SET UP PULSE

OUTPUT FOR

PHASE A, B, OR C

STEP 5

SET UP SYSTEM

FOR ITEST, VNOM

PF = 1

STEP 6

MEASURE %

ERROR FOR APCF

AND VARCF

STEP 7

CALCULATE AND

WRITE TO

XWG, XVAG

CALCULATE Wh/LSB

AND VAh/LSB

CONSTANTS

SET CFNUM/VARCFNUM

AND CFDEN/VARCFDEN

TO CALCULATED VALUES

STEP 4

END

ALL PHASES

VAR GAIN

CALIBRATED?

YES

SELECT VAR

FOR VARCF

OUTPUT

STEP 3

SET UP PULSE

OUTPUT FOR

PHASE A, B, OR C

VARCFNUM/

VARCFDEN

SET TO CALCULATED

VALUES?

YES

STEP 5

SET UP SYSTEM

FOR ITEST, VNOM

PF = 0

STEP 6

MEASURE %

ERROR FOR

VARCF

STEP 7

CALCULATE AND

WRITE TO XVARG

CALCULATE

kVARh/LSB

CONSTANT

SET

VARCFNUM/VARCFDEN TO

CALCULATED VALUES

STEP 4

Figure 77. Gain Calibration Using Pulse Output

Step 1: Enable the pulse output by setting Bit 2 of the OPMODE

VARCF pulses.

Step 1a: VAR and VA share the VARCF pulse output.

WAVMODE[7], Address (0x15), should be set to choose

between VAR or VA pulses on the output. Setting the bit to Logic

1 selects VA. The default is Logic 0 or VARCF pulse output.

Step 2: Ensure the xWG/xVARG/xVAG are set to Logic 0.

Step 3: Disable the Phase B and Phase C contribution to the

APCF and VARCF pulses. This is done by the TERMSEL[2:4]

bits of the COMPMODE register (0x16). Setting Bit 2 to Logic 1

and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included

in the pulse outputs.

Step 4: Set APCFNUM(0x45) and APCFDEN(0x46) to the

calculated value to perform a coarse adjustment on the

imp/kWh ratio. For VAR/VA calibration, VARCFNUM (0x47)

and VARCFDEN(0x48) should be set to the calculated value.

The pulse output frequency with one phase at full-scale inputs

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