ADE7758 datasheet(65/68 Pages) AD

65 / 68 page

ADE7758

Rev. A | Page 65 of 68

INTERRUPT MASK REGISTER (0x18)

When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the

MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table 19 describes the

function of each bit in the interrupt mask register.

Table 19. Function of Each Bit in the Interrupt Mask Register

Bit

Location

Interrupt

Flag

Default

Value

Description

AEHF

Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers,

i.e., the WATTHR register is half full.

REHF

Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers,

i.e., the VARHR register is half full.

VAEHF

Enables an interrupt when there is a 0 to 1 transition in the MSB of any one of the three VAHR

registers, i.e., the VAHR register is half full.

SAGA

Enables an interrupt when there is a SAG on the line voltage of the Phase A.

SAGB

Enables an interrupt when there is a SAG on the line voltage of the Phase B.

SAGC

Enables an interrupt when there is a SAG on the line voltage of the Phase C.

ZXTOA

Enables an interrupt when there is a zero-crossing timeout detection on Phase A.

ZXTOB

Enables an interrupt when there is a zero-crossing timeout detection on Phase B.

ZXTOC

Enables an interrupt when there is a zero-crossing timeout detection on Phase C.

ZXA

Enables an interrupt when there is a zero crossing in the voltage channel of Phase A (see the

Zero-Crossing Detection section).

ZXB

Enables an interrupt when there is a zero crossing in the voltage channel of Phase B (see the

Zero-Crossing Detection section).

ZXC

Enables an interrupt when there is a zero crossing in the voltage channel of Phase C (see the

Zero-Crossing Detection section).

LENERGY

Enables an interrupt when the energy accumulations over LINECYC are finished.

RESERVED

Reserved.

PKV

Enables an interrupt when the voltage input selected in the MMODE register is above the value

in the PKVLVL register.

PKI

Enables an interrupt when the current input selected in the MMODE register is above the value

in the PKILVL register.

WFSM

Enables an interrupt when data is present in the WAVEMODE register.

REVPAP

Enables an interrupt when there is a sign change in the watt calculation among any one of the

phases specified by the TERMSEL bits in the COMPMODE register.

REVPRP

Enables an interrupt when there is a sign change in the VAR calculation among any one of the

phases specified by the TERMSEL bits in the COMPMODE register.

SEQERR

Enables an interrupt when the zero crossing from Phase A is not followed by the zero crossing

of Phase C but with that of Phase B.

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