ADE7758

Rev. A | Page 7 of 68

TIMING CHARACTERISTICS1, 2

Table 2.

Parameter

Specification

Unit

Test Conditions/Comments

Write Timing

50

ns (min)

CS falling edge to first SCLK falling edge.

50

ns (min)

SCLK logic high pulse width.

50

ns (min)

SCLK logic low pulse width.

10

ns (min)

Valid data setup time before falling edge of SCLK.

5

ns (min)

Data hold time after SCLK falling edge.

900

ns (min)

Minimum time between the end of data byte transfers.

50

ns (min)

Minimum time between byte transfers during a serial write.

100

ns (min)

CS hold time after SCLK falling edge.

Read Timing

1.1

µs (min)

Minimum time between read command (i.e., a write to communication register) and data read.

50

ns (min)

Minimum time between data byte transfers during a multibyte read.

30

ns (min)

Data access time after SCLK rising edge following a write to the communications register.

100

ns (max)

Bus relinquish time after falling edge of SCLK.

10

ns (min)

100

ns (max)

Bus relinquish time after rising edge of CS.

10

ns (min)

(10% to 90%) and timed from a voltage level of 1.6 V.

and

and the

section.

Figure 3

Figure 4

ADE7758 Serial Interface

and defined as the time required for the output to cross 0.8 V or 2.4 V.

Figure 2

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

200

µAI

OL

1.6mA

2.1V

TO OUTPUT

PIN

50pF

Figure 2. Load Circuit for Timing Specifications