ADE7758 datasheet(26/68 Pages) AD

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ADE7758

Rev. A | Page 26 of 68

PERIOD MEASUREMENT

The ADE7758 provides the period or frequency measurement

of the line voltage. The period is measured on the phase

specified by Bit 0 to Bit 1 of the MMODE register. The period

every 4 periods of the selected phase.

Bit 7 of the LCYCMODE selects whether the period register

displays the frequency or the period. Setting this bit to logic

high causes the register to display the period. The default

setting is logic low, which causes the register to display the

frequency.

When set to measure the period, the resolution of this register is

96/CLKIN per LSB (9.6 µs/LSB when CLKIN is 10 MHz),

which represents 0.06% when the line frequency is 60 Hz. At 60

Hz, the value of the period register is 1737d. At 50 Hz, the value

of the period register is 2084d. When set to measure frequency,

the value of the period register is approximately 960d at 60 Hz

and 800d at 50 Hz. This is equivalent to 0.0625 Hz/LSB.

LINE VOLTAGE SAG DETECTION

The ADE7758 can be programmed to detect when the absolute

value of the line voltage of any phase drops below a certain peak

value, for a number of half cycles. Each phase of the voltage

channel is controlled simultaneously. This condition is

illustrated in Figure 57.

SAGLVL[7:0]

FULL-SCALE

READ RSTATUS

SAGCYC[7:0] = 0x06

6HALF CYCLES

SAG INTERRUPT FLAG

(BIT 3 TO BIT 5 OF

STATUS REGISTER)

VAP, VBP, OR VCP

SAG EVENT RESET LOW

WHEN VOLTAGE CHANNEL

EXCEEDS SAGLVL[7:0]

Figure 57. ADE7758 SAG Detection

Figure 57 shows a line voltage fall below a threshold which is set

in the SAG level register (SAGLVL[7:0]) for nine half cycles.

Since the SAG cycle register indicates a six half-cycle threshold

(SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of

the sixth half cycle by setting the SAG flag of the corresponding

phase in the interrupt status register (Bit 1 to Bit 3 in the

interrupt status register). If the SAG enable bit is set to Logic 1

for this phase (Bit 1 to Bit 3 in the interrupt mask register), the

IRQ logic output goes active low (see the ADE7758 Interrupts

section). The phases are compared to the same parameters

defined in the SAGLVL and SAGCYC registers.

SAG LEVEL SET

The contents of the single-byte SAG level register, SAGLVL[0:7],

are compared to the absolute value of Bit 6 to Bit 13 from the

voltage waveform samples. For example, the nominal maximum

code of the voltage channel waveform samples with a full-scale

signal input at 60 Hz is 0x249C (see the Voltage Channel

Sampling section). Bit 13 to Bit 6 are 0x92. Therefore, writing

0x92 to the SAG level register puts the SAG detection level at

full scale and sets the SAG detection to its most sensitive value.

The detection is made when the content of the SAGLVL[7:0]

the SAG detection level at 0. The detection of a decrease of an

input voltage is in this case disabled.

PEAK VOLTAGE DETECTION

The ADE7758 can record the peak of the voltage waveform and

produce an interrupt if the current exceeds a preset limit.

Peak Voltage Detection Using the VPEAK Register

The peak absolute value of the voltage waveform within a fixed

number of half-line cycles is stored in the VPEAK register.

Figure 58 illustrates the timing behavior of the peak voltage

detection.

CONTENT OF

VPEAK[7:0]

NO. OF HALF

LINE CYCLES

SPECIFIED BY

LINECYC[15:0]

VOLTAGE WAVEFORM

(PHASE SELECTED BY

PEAKSEL[2:4]

IN MMODE REGISTER)

Figure 58. Peak Voltage Detection Using the VPEAK Register

Note that the content of the VPEAK register is equivalent to Bit 6

to Bit 13 of the 16-bit voltage waveform sample. At full-scale

analog input, the voltage waveform sample at 60 Hz is 0x249C.

The VPEAK at full-scale input is, therefore, expected to be 0x92.

In addition, multiple phases can be activated for the peak

detection simultaneously by setting multiple bits to logic high

among the PEAKSEL[2:4] bits in the MMODE register. These

bits select the phase for both voltage and current peak measure-

ments. Note that if more than one bit is set, the VPEAK and

IPEAK registers can hold values from two different phases, i.e.,

the voltage and current peak are independently processed (see

the Peak Current Detection section).

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