ADE7758 datasheet(27/68 Pages) AD

27 / 68 page

ADE7758

Rev. A | Page 27 of 68

Note that the number of half-line cycles is based on counting

the zero crossing of the voltage channel. The ZXSEL[2:0] bits in

the LCYCMODE register determine which voltage channels are

used for the zero-crossing detection. The same signal is also

used for line cycle energy accumulation mode if activated (see

the Line Cycle Accumulation Mode Register (0x17) section).

Overvoltage Detection Interrupt

Figure 59 illustrates the behavior of the overvoltage detection.

VPINTLVL[7:0]

READ RSTATUS

PKV INTERRUPT FLAG

(BIT 14 OF STATUS

PKV RESET LOW

WHEN RSTATUS

VOLTAGE PEAK WAVEFORM BEING MONITORED

(SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER)

Figure 59. ADE7758 Overvoltage Detection

Note that the content of the VPINTLVL[7:0] register is

equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform

samples; therefore, setting this register to 0x92 represents

putting the peak detection at full-scale analog input. Figure 59

shows a voltage exceeding a threshold. By setting the PKV flag

(Bit 14) in the interrupt status register, the overvoltage event is

recorded. If the PKV enable bit is set to Logic 1 in the interrupt

mask register, the IRQ logic output goes active low (see the

ADE7758 Interrupts section).

Multiple phases can be activated for peak detection. If any

of the active phase produces waveform samples above the

threshold, the PKV flag in the interrupt status register is set.

The phase in which overvoltage is monitored is set by the

PKIRQSEL[5:7] bits in the MMODE register (see Table 15).

PHASE SEQUENCE DETECTION

The ADE7758 has on-chip phase sequence error detection

interrupt. If the zero crossing of Phase A is not followed by

Phase C but by Phase B, the SEQERR bit (Bit 19) in the STATUS

IRQ logic output goes active low (see the ADE7758 Interrupts

section). The following figure depicts how the interrupt is

issued in two different configurations. Note that if it is desired

to have the interrupt occur when Phase A is followed by

Phase B and not Phase C, then the analog inputs for Phase B

and phase C should be swapped. In this case, the Phase B

voltage input should be wired to the VCP pin and the phase C

voltage input should be wired to the VBP pin.

VOLTAGE

WAVEFORMS

ZERO

CROSSINGS

VOLTAGE

WAVEFORMS

ZERO

CROSSINGS

SEQERR BIT OF STATUS REGISTER IS SET

SEQERR BIT OF STATUS REGISTER IS NOT SET

A = 0

°C

B = –120

°C

C = 120

°C

A = 0

°C

C = –120

°C

B = 120

°C

Figure 60. Phase Sequence Detection

POWER-SUPPLY MONITOR

The ADE7758 also contains an on-chip power-supply monitor.

The analog supply (AVDD) is monitored continuously by the

ADE7758. If the supply is less than 4 V ± 5%, the ADE7758

goes into an inactive state, that is, no energy is accumulated

when the supply voltage is below 4 V. This is useful to ensure

correct device operation at power-up and during power-down.

The power-supply monitor has built-in hysteresis and filtering.

This gives a high degree of immunity to false triggering due to

noisy supplies. Figure 61 shows the behavior of the ADE7758

when the voltage of AVDD falls below the power-supply

monitor threshold. The power supply and decoupling for the

part should be designed such that the ripple at AVDD does not

exceed 5 V ± 5% as specified for normal operation.

AVDD

ADE7758

INTERNAL

CALCULATIONS

ACTIVE

INACTIVE

TIME

Figure 61. On-Chip Power-Supply Monitoring

ADE7758 数据表(PDF) 27 Page - Analog Devices

ADE7758 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载