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TUSB7340 数据表(PDF) 32 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 32 Page - Texas Instruments |
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32 / 117 page  TUSB7320, TUSB7340 SLLSE76M – MARCH 2011 – REVISED JULY 2015 www.ti.com Table 38. Power Management Control/Status Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION No Soft Reset. This bit returns 1 indicating that no internal reset is 3 NO_SOFT_RESET r generated and the device retains its configuration context when transitioning from the D3hot state to the D0 state. 2 RSVD r Reserved. Returns zero when read. Power State. This 2-bit field is used both to determine the current power state of the function and to set the function into a new power 1:0 PWR_STATE rw state. This field is encoded as follows:00 = D001 = D110 = D211 = D3hot. 7.5.1.26 Power Management Bridge Support Extension Register This read-only register is not applicable to the TUSB73X0 and returns 00h when read. PCI register offset: 46h Register type: Read-only Default value: 00h Table 39. PCI Register 46h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 32 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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