TUSB7340 datasheet(7/117 Pages) TI1

7 / 117 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76M – MARCH 2011 – REVISED JULY 2015

Clock and Reset Signals (continued)

I/O

DESCRIPTION

TUSB7320

TUSB7340

NAME

NO.

JTAG_TMS

B30

JTAG test mode select

JTAG_RST#

B32

JTAG reset. Should be pulled low for normal operation.

I/O

GPIO0

A49

I/O

GPIO1

B46

General purpose I/O

I/O

GPIO2

B47

I/O

GPIO3

B48

System management interrupt

SMI

Note: This pin is active high and should not be pulled up/down.

R1EXT

A24

High precision external resistor used for calibration. A resister value of 9.09 K

Ω ±1% accuracy is

connected between the terminals R1EXT and R1EXTRTN.

R1EXTRTN

B23

Auxiliary power detect. This pin indicates if the TUSB73X0 is enabled for wakeup from D3cold.

AUX_DET

A52

Note: If this feature is implemented, AUX_DET must be pulled to VDD33 to prevent leakage.

B4, A5, B5,

B6, A7, B7,

A8, B8,

B13, A14,

B25, A26,

A14, B8,

Pins are not connected internally.

B26, A27,

B13, A26,

I/O

Note: TUSB7320 pins B4 and B26 may be connected to VDDA_3P3 to support a dual-layout option

B27, B28,

B29, A43

with the TUSB7340.

A29, B29,

A30, A43,

B43, B45,

A46, A48

POWER SIGNALS

A3, A34,

VDD33

A39, A47,

3.3-V I/O power rail

A51

B4, B11,

B11, A19,

A19, A21,

VDDA_3P3

A21, A25,

3.3-V analog power rail

A25, B22,

B22, A44

B26, A44

A1, B1, A4,

A6, A9,

A12, A16,

B17, B19,

VDD11

B24, A28,

1.1-V core power rail

A33, A31,

A38, B37,

B40, B42,

B44, A50

VSS

B20, A53

Ground. The ground pad is labeled A53 for schematic purposes.

C1, C2, C3,

The corner pins, which are for mechanical stability of the package, are connected to ground internally.

VSS_NC

These pins may be connected to VSS or left unconnected.

Oscillator return.

If using a crystal, the load capacitors should use this signal as the return path and it should not be

VSS_OSC

B21

connected to the PCB ground.

If using an oscillator, this should be connected to PCB Ground.

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