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TUSB7340 数据表(PDF) 65 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 65 Page - Texas Instruments |
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65 / 117 page  TUSB7320, TUSB7340 www.ti.com SLLSE76M – MARCH 2011 – REVISED JULY 2015 7.5.2.8 Correctable Error Mask Register The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 114h Register type: Read-Only, Read/Write Default value: 0000 2000h Table 122. PCI Express Extended Register 114h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 State Table 123. Bit Descriptions – Correctable Error Mask Register BIT FIELD NAME ACCESS DESCRIPTION 31:14 RSVD r Reserved. Returns zeros when read. Advisory Non-Fatal Error Mask. 13 ANFEM(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked Replay Timer Timeout Mask. 12 REPLAY_TMOUT_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 11:9 RSVD r Reserved. Returns zeros when read. REPLAY_NUM Rollover Mask. 8 REPLAY_ROLL_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked Bad DLLP Error Mask. 7 BAD_DLLP_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked Bad TLP Error Mask. 6 BAD_TLP_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked 5:1 RSVD r Reserved. Returns zeros when read. Receiver Error Mask. 0 RX_ERROR_MASK(1) rw 0 – Error Condition is Unmasked 1 – Error Condition is Masked (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on reset. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Links: TUSB7320 TUSB7340 |
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