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TUSB7340 数据表(PDF) 80 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 80 Page - Texas Instruments |
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80 / 117 page  TUSB7320, TUSB7340 SLLSE76M – MARCH 2011 – REVISED JULY 2015 www.ti.com Table 162. Port Status and Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 26 WDE(1) rw Wake on Disconnect Enable. 25 WCE(1) rw Wake on Connect Enable. 24 RSVD r Reserved. Return zero when read. Port Config Error Change. This field is only valid for USB 3.0 protocol 23 CEC(1) rc or r ports. For USB 2.0 protocol ports, this bit is reserved. 22 PLC(1) rc Port Link State Change. 21 PRC(1) rc Port Reset Change. 20 OCC(1) rc Overcurrent Change. Warm Port Reset Change. This field is only valid for USB 3.0 protocol 19 WRC(1) rc or r ports. For USB 2.0 protocol ports, this bit is reserved. 18 PEC(1) rc Port Enabled/Disabled Change. 17 CSC(1) rc Connect Status Change. 16 LWS w Port Link State Write Strobe. This bit returns a zero when read. Port Indicator Control. Because the TUSB73X0 does not support port 15:14 PIC(1) rw indicators, this field has no effect. 13:10 PORT_SPEED(1) r Port Speed 9 PP(1) rw Port Power. 8:5 PLS(1) rw Port Link State 4 PR(1) rs Port Reset. 3 OCA r Overcurrent Active. 2 RSVD r Reserved. Returns zero when read. 1 PED(1) rc Port Enabled/Disabled. 0 CCS(1) r Current Connect Status. 7.5.3.3.10 Port PM Status and Control Register (USB 3.0 Ports) The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Host Controller Structural Parameters 1). Operational Base register offset: 404h + (10h × (n-1))), where n = Port Number Register type: Read-Only, Read/Write Default value: 0000 0000h Table 163. HC Operational Register (Operational Base + 404h + (10h × (n-1))), where n = Port Number Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Table 164. Port PM Status and Control Register (USB 3.0) Description BIT FIELD NAME ACCESS DESCRIPTION 31:17 RSVD r Reserved. Returns zeros when read. 16 FLA rw Force Link PM Accept. 15:8 U2_TIMEOUT(1) rw U2 Timeout. (1) This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated poweron reset. 80 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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