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TUSB7340 数据表(PDF) 9 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 9 Page - Texas Instruments |
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9 / 117 page  TUSB7320, TUSB7340 www.ti.com SLLSE76M – MARCH 2011 – REVISED JULY 2015 6.4 Thermal Information TUSB7320, TUSB7340 THERMAL METRIC(1) RKM (WQFN-MR) UNIT 100 PINS RθJA Junction-to-ambient thermal resistance 25.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W RθJB Junction-to-board thermal resistance 15.2 °C/W ψJT Junction-to-top characterization parameter 0.1 °C/W ψJB Junction-to-board characterization parameter 7.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 3.3-V I/O Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT VIH High-level input voltage(1) VDD33 2 VDD33 V 0 0.8 VIL Low-level input voltage(1) VDD33 V JTAG pins only 0 0.55 VI Input voltage 0 VDD33 V VO Output voltage(2) 0 VDD33 V tt Input transition time (trise and tfall) 0 25 ns Vhys Input hysteresis(3) 0.13 VDD33 V VOH High-level output voltage VDD33 IOH = -4 mA 2.4 V VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA High-impedance, output current with internal pullup IOZP VDD33 VI = 0 to VDD33 ±225 µA or pulldown resistor(4) II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA (1) Applies to external inputs and bidirectional buffers. (2) Applies to external outputs and bidirectional buffers. (3) Applies to PERST, GRST, and PME. (4) Applies to GRST (pullup) and most GPIO (pullup). (5) Applies to external input buffers. 6.6 Input Clock Specification See External Clock. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Operational Frequency Tolerance ±50 ppm Temperature Frequency Stability 1 year aging ±100 ppm Rise / Fall Time 20% - 80% 6 ns Reference Clock RJ with JTF (1 sigma) (1) (2) 0.8 ps Reference Clock TJ with JTF (total p-p) (2) (3) 25 ps Reference Clock Jitter 50 ps (absolute p-p)(4) (1) Sigma value assuming Gaussian distribution. (2) After application of JTF. (3) Calculated as 14.1 x RJ+DJ (4) Absolute phase jitter (p-p) Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TUSB7320 TUSB7340 |
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