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TUSB7340 数据表(PDF) 79 Page - Texas Instruments

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部件名 TUSB7340
功能描述  USB 3.0 xHCI Host Controller
PDF  117 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TUSB7340 数据表(HTML) 79 Page - Texas Instruments

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TUSB7320, TUSB7340
www.ti.com
SLLSE76M – MARCH 2011 – REVISED JULY 2015
7.5.3.3.8
Configure Register
This register defines runtime xHC configuration parameters.
Operational Base register offset: 38h
Register type: Read-Only, Read/Write
Default value: 0000 0000h
Table 159. HC Operational Register (Operational Base + 38h)
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
No.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
No.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Table 160. Configure Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:8
RSVD
r
Reserved. Returns zeros when read.
7:0
MAX_SLOTS_EN
rw
Max Device Slots Enabled.
7.5.3.3.9
Port Status and Control Register
The TUSB73X0 implements a Port Status and Control Register for each port that is implemented. The number of
Port Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller
Structural Parameters 1 Register (see Host Controller Structural Parameters 1).
Operational Base register offset: 400h + (10h × (n-1))), where n = Port Number
Register type: Read-Only, Read/Write, Read/Clear
Default value: X000 02A0h
Table 161. HC Operational Register (Operational Base + 400h + (10h × (n-1))), where n = Port Number
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
No.
Reset
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
No.
Reset
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
State
Table 162. Port Status and Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
Warm Port Reset. This field is only valid for USB 3.0 protocol ports. For
31
WPR(1)
rc or r
USB 2.0 protocol ports, this bit is reserved.
Device Removable. The value of this bit depends on the value
programmed into the USBx_PORTy_NON_REM bit in the USB Control
30
DR
r
Register that corresponds to the port number and port type associated
with this register.
29:28
RSVD
r
Reserved. Returns zeros when read.
27
WOE(1)
rw
Wake on Overcurrent Enable.
(1)
This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated poweron reset.
Copyright © 2011–2015, Texas Instruments Incorporated
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Product Folder Links: TUSB7320 TUSB7340



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