TVP7002IPZP datasheet(16/58 Pages) TI1

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TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

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Sync Slicer

TVP7002 includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value)

above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The

digital output of the composite sync slicer is available on the SOGOUT pin.

Noise Immunity

In general, noise on a slowly varying input signal (i.e., sync falling edge) may cause a voltage comparator to

false trigger as the input passes through the linear range of the comparator. To improve the overall performance

of the TVP7002 sync slicer in the presence of noise on the SOG input, the voltage comparator includes

hysteresis. Maintaining a 50% slice level using the I2C programmable slice level control can further improve the

noise immunity of the Sync slicer. The slice level is programmable in 11.2-mV increments over a 350-mV range

as follows.

slice_level = (350 mV) × (NTH/31)

where 0

≤ NTH ≤ 31, default: 11

≤ slice_level ≤ 350 mV

Glitch Immunity

During white-to-black transitions, the input video waveform may undershoot below the sync slicer threshold. To

help attenuate the amplitude of such glitches, a single-pole low-pass filter with three selectable cutoff frequencies

(2.5, 10, and 33 MHz) is provided at the input of the SOG voltage comparator circuit. This filter is bypassed in the

default mode.

NOTE

Although the low-pass filter may attenuate the amplitude of glitches present on the SOG

input, it also makes the sync falling edge less sharp.

Sync Separator

The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at

the SOG input. The G or Y input containing the composite sync must be ac coupled to the SOG input pin using a

1-nF capacitor. Support for PC graphics, SDTV, EDTV, and HDTV up to 1080p is provided. The internal sync

separator provides support for formats having field rates (VSYNC frequencies) at or above 40 Hz. An external

sync separator or separated VSYNC must be used for field rates less than 40 Hz.

Sync Activity Detection

The TVP7002 provides activity detection on the sync inputs (VSYNC, HSYNC) to enable the host processor to

determine whether the PC graphics source is configured as a 3-wire, 4-wire, or 5-wire interface as defined here:

•

5 wire (G, B, R, HSYNC, VSYNC)

•

4 wire (G, B, R, CSYNC)

•

3 wire (G, B, R with SOG)

If activity is detected on the VSYNC input, the host processor should assume that the PC graphics input is a

standard 5-wire interface. In this case, the HSYNC input of the TVP7002 should be configured as an HSYNC

input. If AHSO and AVSO are set for automatic selection in I2C Reg 0Eh, the TVP7002 will automatically use the

HSYNC and VSYNC inputs, provided signals are present at both inputs.

If activity is detected on the HSYNC input but not on the VSYNC input, the host processor should assume that

the PC graphics input is a standard 4-wire interface. In this case, the HSYNC input of the TVP7002 should be

used as a digital CSYNC input. If AHSO and AVSO are set for automatic selection, VSYNC will be properly

decoded from the CSYNC input, provided no signal is present at the VSYNC input pin. Some test sources output

CSYNC on both the HSYNC pin and the VSYNC pin. In this case, the active VSYNC source (AVSS) must be

manually set to Sync separated VSYNC in Reg 0Eh.

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