TVP7002IPZP datasheet(13/58 Pages) TI1

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COAST

HSYNC

Phase

Detector

PLL Control

Bit [5:3]

PLL Control

Bit [7:6]

Phase Select

Bit [7:3]

Charge

Pump

VCO

Phase

Select

Divider

ADC

Sampling

CLK

External

Clock

PLL Divide

1:0]

Bit [1

Loop

Filter

N = 1 or 2

Post

Divider

÷N

Post Divider

Bit [0]

TVP7002

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SLES206C – MAY 2007 – REVISED APRIL 2013

Automatic Level Control (ALC)

The ALC circuit maintains the level of the signal to be set at a value that is programmed at the fine offset I2C

the I2C register at subaddress 26h.

The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The

ALC pulse must be positioned after the clamp pulse. The position of ALC pulse is controlled by ALC placement

I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp

pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is

recommended to keep the external clamp pulse as long as possible.

Analog-to-Digital Converters (ADCs)

All ADCs have a resolution of 10 bits and can operate up to 165 MSPS. All A/D channels receive an identical

clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 165 MHz. All ADC

reference voltages are generated internally. Also the external sampling clock can be used.

Horizontal PLL

The horizontal PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to

derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal

sync signal supplied on the HSYNC input or from extracted horizontal sync of the sync slicer block for embedded

sync signals. The horizontal PLL consists of a phase detector, charge pump, loop filter, voltage controlled

oscillator (VCO), phase select, feedback divider, and post divider. The horizontal PLL block diagram is shown in

Figure 3.

Figure 3. Horizontal PLL Block Diagram

The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the

incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other

time that the HSYNC is not available.

There are several PLL controls to produce the correct sampling clock. The 12-bit feedback divider register is

programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to

165 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-

pass loop filter. The applicable current values are listed in the Table 4.

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