TVP7002IPZP datasheet(11/58 Pages) TI1

11 / 58 page

TVP7002

www.ti.com

SLES206C – MAY 2007 – REVISED APRIL 2013

FUNCTIONAL DESCRIPTION

Analog Channel

The TVP7002 contains three identical analog channels that are independently programmable. Each channel

consists of a clamping circuit, programmable gain control, programmable offset control, and an ADC.

Analog Input Switch Control

TVP7002 has three analog channels that accept up to ten video inputs. The user can configure the internal

analog video switches via the I2C interface. The ten analog video inputs can be used for different input

configurations, some of which are:

•

Up to three SDTV, EDTV, or HDTV component video inputs (limited by number of SOG inputs)

•

Up to two 5-wire PC graphics inputs (limited by number of HSYNC and VSYNC inputs)

The input selection is performed by the input select register at I2C subaddress 19h a 1Ah (see Input

Mux Select 1 and Input Mux Select 2).

Supported Video Formats

The TVP7002 supports A/D conversion of SDTV (480i, 576i), EDTV (480p, 576p), and HDTV (720p, 1080i,

1080p) YPbPr component video inputs. The TVP7002 also supports A/D conversion and color space conversion

of all standard PC graphics formats (RGB) from VGA up to UXGA. The internal sync separator provides support

for field rates (VSYNC frequencies) at or above 40 Hz. Separated VSYNC or an external sync separator must be

used to support formats having field rates less than 40 Hz. A summary of the analog video standards supported

by the TVP7002 module is show in Table 2.

Table 2. Analog Video Standards

VIDEO FORMAT

VIDEO STANDARDS

SDTV (YPbPr component)

480i, 576i

EDTV (YPbPr component)

480p, 576p

720p50, 720p60, 1080i50,

HDTV (YPbPr component)

1080i60, 1080p50, 1080p60

PC graphics (RGB component)

VGA to UXGA

SCART (RGB component)

576i

Analog Input Clamping

The TVP7002 provides dc restoration for all analog video inputs including the SOG slicer inputs. The dc

restoration circuit (a.k.a. clamp circuit) restores the ac-coupled video signal to a fixed dc level. One dc restoration

circuit is implemented prior to each of the three ADCs, and a fourth one is located prior to the SOG slicer. The dc

restoration circuit can be programmed to operate as either a sync-tip clamp (a.k.a. coarse clamp) or a back-

porch clamp (a.k.a. fine clamp). The sync-tip clamp always clamps the video sync-tip level near the bottom of the

ADC range. The back-porch type clamp supports two clamping levels (bottom level and mid level) that are

selectable using bits 0, 1, and 2 of register 10h. When using the fine bottom-level clamp, an optional 300-mV

common-mode offset may be selected using bit 7 of register 2Ah.

In general, the analog video input being used for horizontal synchronization purposes should always use the

sync-tip clamp; all other analog video inputs should use the back-porch clamp. The advantage of the back-porch

clamp is that it has negligible video droop or tilt across a video line.

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