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TVP7002IPZP 数据表(PDF) 37 Page - Texas Instruments |
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TVP7002IPZP 数据表(HTML) 37 Page - Texas Instruments |
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37 / 58 page ![]() TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Input Mux Select 2 Subaddress 1Ah Default (C2h) 7 6 5 4 3 2 1 0 SOG LPF SEL [1:0] CLP LPF SEL [1:0] CLK SEL VS SEL PCLK SEL HS SEL SOG LPF SEL [1:0]: SOG low-pass filter selection. The SOG low-pass filter can be used to attenuate glitches present on the SOG input. Excessive filtering can lead to sync detection issues and increased sample clock jitter. 00 = 2.5-MHz low-pass filter 01 = 10-MHz low-pass filter 10 = 33-MHz low-pass filter 11 = Low-pass filter bypass (default) CLP LPF SEL [1:0]: Coarse clamp low-pass filter selection. This filter effects the operation of all enabled coarse clamps which is generally the SOG coarse clamp only. 00 = 4.8-MHz low-pass filter (default). Suitable for HDTV and graphics formats. 01 = 0.5-MHz low-pass filter. Suitable for SDTV formats. 10 = 1.7-MHz low-pass filter 11 = Reserved CLK SEL: Clock reference select for Sync Processing block. The internal reference clock is typically 6.5 MHz, but it should not be considered a precise clock. An external 27-MHz reference clock is therefore recommended for accurate mode detection. NOTE: The I2C interface, Sync Separator, and activity detection circuitry always uses the internal clock reference. 0 = Internal clock reference (default) 1 = External clock reference (EXT_CLK) NOTE: The external clock input can also be selected as the sample clock for the ADCs (see bit 1). VS SEL: VSYNC input select 0 = VSYNC_A input selected (default) 1 = VSYNC_B input selected PCLK SEL: Pixel clock selection. When the external clock input (pin 80) is selected as the ADC sample clock, the external clamp pulse (pin 76) should also be selected (Bit 7 of subaddress 0Fh). 0 = ADC samples data using external clock input (pin 80) 1 = ADC samples data using H-PLL generated clock (default) NOTE: The external clock input can also be selected as the reference clock for the Sync Processing block (see bit 3). HS SEL: HSYNC input select 0 = HSYNC_A input selected (default) 1 = HSYNC_B input selected NOTE: See the Sync Control register at subaddress 0Eh. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links: TVP7002 |
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