TVP7002IPZP datasheet(34/58 Pages) TI1

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TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

www.ti.com

Output Formatter

Subaddress

15h

Default (04h)

Reserved

Output code range [1:0]

Reserved

Clamp REF

CbCr order

422/444

Sync En

Reserved [7]:

0 = Required (default)

Output code range [1:0]:

00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default)

01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019)

10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)

11 = Reserved

Reserved [4]:

0 = Required (default)

Clamp REF: Selects which edge of HSYNC is used as the timing reference for the fine clamp pulse placement and also the ALC

placement.

0 = Clamp pulse placement referred to the trailing edge of HSYNC (default)

1 = Clamp pulse placement referred to the leading edge of HSYNC

CbCr order: This bit is only effective in the 4:2:2 output mode (i.e., bit 1 is set to 1).

0 = CbCr order

1 = CrCb order (default)

422/444: Active-high 4:4:4 to 4:2:2 decimation filter enable

0 = 30-bit 4:4:4 output format (default)

1 = 20-bit 4:2:2 output format

Notes:

1. Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.

2. 10-bit 4:2:2 output format is not supported.

Sync En: Active-high embedded sync enable

0 = Embedded sync disabled (default)

1 = Embedded sync enabled

Notes:

1. Embedded syncs are not supported when the RGB coding range (0 to 1023) is selected.

2. Embedded syncs are not supported when the 30-bit 4:4:4 output format is selected.

3. Discrete syncs are always enabled except when outputs are placed in the high-impedance mode.

4. When enabled, embedded syncs are present in both the Y and C outputs.

MISC Control 1

Subaddress

16h

Default (11h)

Reserved

CbCr Align

Reserved

PLL PD

STRTB

CbCr Align: CbCr alignment

0 = Alternative operation

1 = Normal operation (default)

PLL PD: Active-high H-PLL power down

0 = Normal operation (default)

1 = H-PLL powered down

STRTB: Active-high H-PLL start-up circuit enable

0 = H-PLL start-up circuit disabled

1 = H-PLL start-up circuit enabled (default)

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TVP7002IPZP 数据表(PDF) 34 Page - Texas Instruments

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