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TVP7002IPZP 数据表(PDF) 8 Page - Texas Instruments |
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TVP7002IPZP 数据表(HTML) 8 Page - Texas Instruments |
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8 / 58 page  TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 0°C to 70°C (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT Analog Interface Input voltage range By design 0.5 1 2 Vpp ZI Input impedance, analog video inputs By design 500 k Ω Digital Logic Interface CI Input capacitance By design 10 pF ZI Input impedance By design 500 k Ω VOH Output voltage high IOH = 2 mA 0.8 IOVDD V VOL Output voltage low IOL = –2 mA 0.2 IOVDD V VOH_SCLK DATACLK output voltage high IOH = 4 mA 0.8 IOVDD V VOL_SCLK DATACLK output voltage low IOH = –4 mA 0.2 IOVDD V VIH High-level input voltage By design 0.7 IOVDD V VIL Low-level input voltage By design 0.3 IOVDD V ADCs ADC full-scale input range Clamp disabled 0.95 1 1.05 Vpp ADC resolution 10-bit range 10 bits 10 bit, 110 MHz, BC = 5 –1 ±0.5 +1 DNL DC differential nonlinearity LSB 8 bit, 162 MHz, BC = 8 –1 ±0.5 +1 10 bit, 110 MHz, BC = 5 –4 ±1 +4 INL DC integral nonlinearity LSB 8 bit, 162 MHz, BC = 8 –4 ±1 +4 10 bit, 110 MHz, BC = 5 none Missing code 8 bit, 162 MHz, BC = 8 none SNR Signal-to-noise ratio 10 MHz, 1 VP-P at 110 MSPS 55 dB Analog 3-dB bandwidth By design 350 500 MHz Horizontal PLL Clock jitter 500 ps Phase adjustment 11.6 degree VCO frequency range By design 12 162 MHz Analog ADC Channel Coarse gain full-scale control range Gain control value NG = 15 ±6 dB Coarse offset full-scale control range Referred to 10-bit ADC output ±124 counts Coarse offset step size Referred to 10-bit ADC output 4 counts Sync Processing Internal clock reference frequency By design 6.5 MHz (1) BC = ADC bias control setting in I2C register, 2Ch 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: TVP7002 |
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