LSM330 datasheet(33/75 Pages) STMICROELECTRONICS

33 / 75 page

DocID023426 Rev 3

33/75

LSM330

Digital interfaces

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a high-to-low transition on the data line while the SCL line is held high. After this

has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits, and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line low so that it

remains stable low during the high period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded in the LSM330 behaves like a slave device and the following protocol

must be adhered to. After the start condition (ST), a slave address is sent. Once a slave

acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7

LSb represent the actual register address while the MSb enables address auto increment. If

the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased to

allow multiple data read/write.

Data is transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of

bytes sent per transfer is unlimited. Data is transferred with the most significant bit (MSb)

first. If a receiver cannot receive another complete byte of data until it has performed some

other function, it can hold the clock line, SCL, low to force the transmitter into a wait state.

Data transfer only continues when the receiver is ready for another byte and releases the

data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to

receive because it is performing some real-time function) the data line must be left high by

Table 11. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 12. Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 13. Transfer when master is receiving (reading) one byte of data from slave

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W

SUB

SR SAD+R

MAK

NMAK SP

Slave

SAK

SAK DATA

DATA

LSM330 数据表(PDF) 33 Page - STMicroelectronics

LSM330 数据表(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

数据表下载

链接网址

LSM330 数据表(PDF) 33 Page - STMicroelectronics

LSM330 数据表(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

数据表 下载

链接网址

数据表下载