LSM330 datasheet(48/75 Pages) STMICROELECTRONICS

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LSM330

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DocID023426 Rev 3

8.14

STAT (18h)

Interrupt synchronization register (r).

8.15

VFC_1 (1Bh)

Vector coefficient register 1 for DIff filter (r/w).

8.16

VFC_2 (1Ch)

Vector coefficient register 2 for DIff filter (r/w).

Table 38. STAT register

LONG

SYNCW

SYNC1

SYNC2

INT_SM1

INT_SM2

DOR

DRDY

Table 39. STAT register description

LONG

LC interrupt flag.

0 = no interrupt; 1 = Long Counter (LC) interrupt flag common for both SM

SYNCW

Synchronization for external host controller interrupt based on output data

0 = no action waiting from host; 1 = action from host based on output data

SYNC1

0 = SM1 running normally; 1 = SM1 stopped and wait restart request from SM2

SYNC2

0 = SM2 running normally; 1 = SM2 stopped and wait restart request from SM1

INT_SM1

SM1- interrupt selection.

1 = SM1 interrupt generated; 0 = SM1 interrupt not generated

NT_SM2

SM2- interrupt selection.

1= SM2 interrupt generated; 0 = SM2 interrupt not generated

DOR

Data overrun indicates data not read from output register when the measurement of

the next data samples starts. 0 = no overrun; 1 = data overrun

data overrun bit is reset when next sample is ready

DRDY

data ready from output register.

0 = data not ready; 1 = data ready

Table 40. VFC_1 default values

00000000

Table 41. VFC_2 default values

00000000

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