STGAP1STR datasheet(9/67 Pages) STMICROELECTRONICS

9 / 67 page

DocID027190 Rev 3

9/67

STGAP1S

Pin connection

Figure 2. Pin connection (top view)

Table 1. Pin description

Pin no.

Pin name

Type

Function

VDD

Power supply

Internal 3.3 V regulator input supply pin

VREG

Power supply

Internal 3.3 V regulator output and supply pin

Logic input

Shutdown input (active low)

IN+

Logic input

Gate command input

IN-/DIAG2

Logic input/open drain output

Gate command input /open drain diagnostic

output

DIAG1

Open drain output

Open drain diagnostic output

1, 12

GND

Ground

Low voltage section ground

4CS

Logic input

SPI chip select (active low)

Logic input

SPI clock

SDI

Logic input

SPI serial data input

SDO

Logic output

SPI serial data output

VCECLAMP

Analog input

VCE active clamping protection

DESAT

Analog input

Desaturation protection

VREGISO

Power supply

Internal regulator output pin for decoupling

Power supply

Positive voltage supply

GON

Analog output

Gate source output

GOFF

Analog output

Gate sink output

CLAMP

Analog output

Miller clamp

SDI

SDO

GND

CLAMP

ASC

DESAT

VCECLAMP

GON

IN+

GOFF

VDD

GND

VREG

VREGISO

SENSE

GNDISO

DIAG1

IN-/DIAG2

STGAP1STR 数据表(PDF) 9 Page - STMicroelectronics

STGAP1STR 数据表(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载

链接网址

STGAP1STR 数据表(PDF) 9 Page - STMicroelectronics

STGAP1STR 数据表(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表 下载

链接网址

数据表下载