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ENICSF2811PBKA 数据表(PDF) 154 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 154 Page - Texas Instruments |
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154 / 172 page  Bit 0 Bit 0 CLKX FSX DX DR M35 M37 M40 M39 M38 M34 LSB MSB M41 M42 Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-3) (n-4) (n-4) TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns M42 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG. For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P ns Disable time, DX high impedance following last data bit M37 tdis(CKXL-DXHZ) P + 6 7P + 6 ns from CLKX low M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG. For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 154 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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