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ENICSF2811PBKA 数据表(PDF) 155 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 155 Page - Texas Instruments |
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155 / 172 page  M51 M50 M47 CLKX FSX DX DR M44 M48 M49 M43 LSB MSB M52 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www.ti.com SPRS174T – APRIL 2001 – REVISED MAY 2012 Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1) MASTER SLAVE NO. UNIT MIN MAX MIN MAX M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns M52 tc(CKX) Cycle time, CLKX 2P 16P ns (1) 2P = 1/CLKG. For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) MASTER SLAVE NO. PARAMETER UNIT MIN MAX MIN MAX M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P ns M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns Disable time, DX high impedance following last data bit M47 tdis(FXH-DXHZ) 6 6P + 6 ns from FSX high M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) 2P = 1/CLKG. For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. Figure 6-47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 155 Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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