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ENICSF2811PBKA 数据表(PDF) 150 Page - Texas Instruments |
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ENICSF2811PBKA 数据表(HTML) 150 Page - Texas Instruments |
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150 / 172 page  TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com 6.31 Multichannel Buffered Serial Port (McBSP) Timing 6.31.1 McBSP Transmit and Receive Timing Table 6-50. McBSP Timing Requirements(1)(2) NO. MIN MAX UNIT 1 kHz McBSP module clock (CLKG, CLKX, CLKR) range 20(3) MHz 50 ns McBSP module cycle time (CLKG, CLKX, CLKR) range 1 ms M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns CLKR int 18 M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low ns CLKR ext 2 CLKR int 0 M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext 6 CLKR int 18 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext 2 CLKR int 0 M18 th(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext 6 CLKX int 18 M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext 2 CLKX int 0 M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext 6 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. (3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (20 MHz). 150 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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