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TNETV2685FIBZUT9 数据表(PDF) 103 Page - Texas Instruments |
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TNETV2685FIBZUT9 数据表(HTML) 103 Page - Texas Instruments |
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103 / 191 page ![]() DDR_D00 DDR_D7 DDR_DQM0 DDR_DQS0 DDR_DQS0 DDR_D08 DDR_D15 DDR_DQM1 DDR_DQS1 DDR_DQS1 BED0 BED7 LDM LDQS LDQS BED8 BED15 UDM UDQS UDQS BA0 BA2 A0 A13 CS CAS RAS WE CKE CK CK VREF DDR_D16 DDR_D23 DDR_DQM2 DDR_DQS2 DDR_DQS2 DDR_D24 DDR_D31 DDR_DQM3 DDR_DQS3 DDR_DQS3 DDR_BA0 DDR_BA2 DDR_A00 DDR_A13 DDR_CS0 DDR_CAS DDR_RAS BSDWE DDR_CKE DDR_CLK DDR_CLK DDR_ODT1 DDR_VREF 1kΩ 1% Vio1.8 (A) DDR2 DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 VREF Terminator,ifdesired.Seeterminatorcomments. T T T T T T T T T T T T T T T T T T T T T T T 0.1 µF VREF 0.1 µF 1kΩ 1% 0.1 µF (B) 0.1 µF (B) DDR_ODT0 NC NC ODT DM647/DM648 NC NC NC NC 1kΩ NC NC 1kΩ NC 1kΩ 1kΩ 1kΩ Vio1.8 (A) Vio1.8 (A) TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include: DM647/DM648. B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. C. Vio 1.8 is the power supply for the DDR2 memory interface. Figure 6-12. 16-Bit DDR2 High-Level Schematic Copyright © 2007–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 103 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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