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STM8TL52X4 数据表(PDF) 64 Page - STMicroelectronics |
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STM8TL52X4 数据表(HTML) 64 Page - STMicroelectronics |
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64 / 84 page ![]() Electrical parameters STM8TL52x4 STM8TL53x4 64/84 DocID022344 Rev 7 9.3.9 Communication interfaces Serial peripheral interface (SPI) The parameters given in Table 34 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions summarized in Section 9.3.1 on page 45 , unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 34. SPI characteristics Symbol Parameter Conditions(1) Min. Max. Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 0 8 MHz Slave mode 0 8 tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF - 30 ns tsu(NSS)(2) NSS setup time Slave mode 4 x tMASTER - th(NSS)(2) NSS hold time Slave mode 80 - tw(SCKH)(2) tw(SCKL)(2) SCK high and low time Master mode, fMASTER = 8 MHz, fSCK= 4 MHz 105 145 tsu(MI) (2) tsu(SI)(2) Data input setup time Master mode 30 - Slave mode 3 - th(MI) (2) th(SI)(2) Data input hold time Master mode 15 - Slave mode 0 - ta(SO)(2)(3) Data output access time Slave mode - 3x tMASTER tdis(SO)(2)(4) Data output disable time Slave mode 30 - tv(SO) (2) Data output valid time Slave mode (after enable edge) - 60 tv(MO)(2) Data output valid time Master mode (after enable edge) -20 th(SO)(2) Data output hold time Slave mode (after enable edge) 15 - th(MO)(2) Master mode (after enable edge) 1- 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi Z. |
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