STM8TL52X4 datasheet(70/84 Pages) STMICROELECTRONICS

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Electrical parameters

STM8TL52x4 STM8TL53x4

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Static latch-up



: 3 complementary static tests are required on 6 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to application note AN1181.

9.4

Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 16: General operating conditions on page 45

The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated

using the following equation:

TJmax = TAmax + (PDmax x JA)

Where:



TAmax is the maximum ambient temperature in C

JA is the package junction-to-ambient thermal resistance in C/W



PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)



PINTmax is the product of IDD and VDD, expressed in watts. This is the maximum chip

internal power.



PI/Omax represents the maximum power dissipation on output pins

where:



PI/Omax = (VOL*IOL) + ((VDDVOH)*IOH), 

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in

the application.

Table 39. Electrical sensitivities

Symbol

Parameter

Class

Static latch-up class

Table 40. Thermal characteristics(1)

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

Symbol

Parameter

Value

Unit

JA

Thermal resistance junction-ambient

UFQFPN 48 - 7 x 7 mm

°C/W

Thermal resistance junction-ambient

UFQFPN 28 - 4 x 4 mm

Thermal resistance junction-ambient

TSSOP20

110

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