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STM32L162VC 数据表(PDF) 92 Page - STMicroelectronics |
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STM32L162VC 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 123 page  Electrical characteristics STM32L162VC, STM32L162RC 92/123 DocID022881 Rev 10 ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. Figure 23. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 24. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. |
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