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STM32L162VC 数据表(PDF) 15 Page - STMicroelectronics |
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STM32L162VC 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 123 page ![]() DocID022881 Rev 10 15/123 STM32L162VC, STM32L162RC 46 VDD=VDDA = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(2) Range 1, Range 2 or Range 3 Full speed operation VDD=VDDA = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(2) Range 1, Range 2 or Range 3 Full speed operation 1. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz. 2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V. Table 3. Functionalities depending on the operating power supply range (continued) Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range I/O operation Table 4. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 3 |
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