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STM32F769AI 数据表(PDF) 186 Page - STMicroelectronics

部件名 STM32F769AI
功能描述  Dual mode Quad-SPI
PDF  255 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F769AI 数据表(HTML) 186 Page - STMicroelectronics

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Electrical characteristics
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
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DocID029041 Rev 4
JTAG/SWD timing diagrams
Figure 51. JTAG timing diagram
Table 88. Dynamics characteristics: SWD characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fpp
SWCLK clock frequency
2.7V <VDD< 3.6V
-
-
80
MHz
1/tc(SWCLK)
1.71 <VDD< 3.6V
--
50
tw(SWCLKH)
SCK high and low time
-
TPCLK − 1TPCLK TPCLK + 1
ns
tw(SWCLKL)
tsu(SWDIO) SWDIO input setup time
-
3.5
-
-
th(SWDIO)
SWDIO input hold time
-
0
-
-
tov (SWDIO) SWDIO output valid time
2.7V <VDD< 3.6V
-
11
12
1.71 <VDD< 3.6V
-
11
16.5
toh(SWDIO) SWDIO output hold time
-
9
-
-



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