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ST6380 数据表(PDF) 23 Page - STMicroelectronics |
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ST6380 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 82 page ![]() 23/82 ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont’d) Hardware Activated Watchdog Register (HWDR) Address: D8h - Read/Write Reset Value: 0FEh T1-T6. These are the watchdog counter bits. It should be noted that D7 (T1) is the LSB of the counter and D2 (T6) is the MSB of the counter, these bits are in the opposite order to normal. SR. This bit is set to one during the reset phase and will generate a software reset if cleared to ze- ro. C. This is the watchdog activation bit that is hard- ware set. The watchdog function is always activat- ed independently of changes of value of this bit. The register reset value is FEh (Bit 1-7 set to one, Bit 0 cleared). Figure 18. Hardware Activated Watchdog Working Principle 70 T1 T2 T3 T4 T5 T6 SR C BIT0 VA00190 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 8-BIT DOWN COUNTER OSC-12 RESET D0 D1 D2 D3 D4 D5 D6 D7 |
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