ST6380 datasheet(57/82 Pages) STMICROELECTRONICS

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

4.8.3 Application Notes

1- The OSD character generator is composed of a

dual port video ram and some circuitry. It needs

two input signals VSYNC and HSYNC to synchro-

nize its dedicated oscillator to the TV picture. It

generates 4 output signals, that can be used from

the TV set to generate the characters on the

screen. For instance, they can be used to feed the

SCART plug, providing an adequate buffer to drive

the low impedance (75 ohm) of the SCART inputs.

2 - The Core sees the OSD as a number of RAM

locations (168) plus a certain number of control

registers (8). 175 of these locations are mapped in

one page of the dynamic data ram address range

(0h...3Fh).

The page 5 (20h value loaded into the register

0E8h) is further subdivided in 4 pages (using bits

LS1 and LS0) in order to allow access to all 168

bytes of the OSD RAM within the allowed address

range. According to the value of these two bits we

shall a first line (selected among lines 0, 2, 4 or 6)

mapped onto the 0h-14h address range, and a

second line (selected among lines 1, 3, 5 or 7)

mapped onto the 20h-34h address range.

The global registers in page 5 are accessible at

RAM locations 38h-3Fh, page 5 selected via DR-

BR, regardless of the value of the LS0/LS1 bits.

3 - The video RAM is a dual port ram. That means

that it can be addressed either from the Core or

from the OSD circuitry itself. To reduce the com-

plexity of the circuitry, and thus its cost, some re-

strictions have been introduced in the use of the

OSD.

The Core can access 6 of the global registers

(addresses 38h - 3Dh in page 5) only when the

OSD oscillator is OFF (GE bit not set). Only

the last location (control register 3Fh in page

5) can be addressed at any time. This is the

Global Enable Register, which contains the

GE and ORE bits. If the GE bit is set, the OSD

is on, if it is reset the OSD is off.

The Core can write to the 168 locations of

OSD RAM only when the ORE bit is not set.

This bit must be set before the first active line

of OSD display (which displays characters).

This line follows the VSYNC active period and

is delayed by a time equal to the Vertical Start

display line (64

µs for the usual TV standard).

4 - The timing of the on/off switching of the OSD

oscillator is the following:

GE bit is set. The OSD oscillator will start on

the next VSYNC signal.

GE bit is reset. The OSD oscillator will be im-

mediately switched off.

To avoid a bad visual impression, it is important

that the GE bit is set before the end of the flyback

time when changing characters. This can be done

inside the VSYNC interrupt routine. The following

diagram can explain better: OSD Oscillator ON/

OFF Timing

Figure 32. OSD Oscillator ON/OFF Timing

Notes:A - Picture time: 20 mS in PAL/SECAM.

B - VSYNC interrupt, if enabled.

C - Starting of OSD oscillator, if GE = 1.

D - Flyback time.

When modifying the picture display (i.e.: a bar

graph for an analog control), it is important that the

switching on of the GE bit is done before the end

of the flyback time (D in Figure 32). If the GE bit is

set after the end of the flyback time then the OSD

will not start until the beginning of the next frame.

This results in one frame being lost and will result

in a flicker on the screen. One method to be sure

to avoid the flicker is to wait for the VSYNC inter-

rupt at the start of the flyback; once the VSYNC in-

terrupt is detected, then the GE and ORE bits can

be set to zero, the global control registers

changed, if necessary, and the GE set to one. All

this should occur before the end of the flyback time

in order not to lose a frame. The correct edge of

the interrupt must be chosen. The characters in

RAM can be changed until the last line before the

active screen area and then the ORE bit must be

set.

time

VSYNC

VA00344

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