ST6380 datasheet(43/82 Pages) STMICROELECTRONICS

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

During transmission or reception of data, all ac-

cess to serial data register is therefore disabled.

The reception or transmission of data is started by

setting the BUSY bit to “1”; this will be automatical-

ly reset at the end of the operation. After reset, the

busy bit is cleared to “0”, and the hardware SPI

disabled by clearing bit 0 and bit 1 of SPI control

SPI are “ANDed” to the standard I/O software con-

trolled outputs. If the hardware SPI is in operation

the Port C pins related to the SPI should be config-

ured as outputs using the Data Direction Register

and should be set high. When the SPI is config-

ured as the S-BUS, the three pins PC0, PC1 and

PC3 become the pins SCL, SDA and SEN respec-

tively. When configured as the I2C BUS the pins

PC0 and PC1 are configured as the pins SCL and

SDA; PC3 is not driven and can be used as a gen-

eral purpose I/O pin. In the case of the STD SPI

the pins PC0 and PC1 become the signals CLOCK

and DATA, PC3 is not driven and can be used as

general purpose I/O pin. The VERIFY bit is availa-

ble when the SPI is configured as either S-BUS or

I2C BUS. At the start of a byte transmission, the

verify bit is set to one. If at any time during the

transmission of the following eight bits, the data on

the SDA line does not match the data forced by the

SPI (while SCL is high), then the VERIFY bit is re-

set. The verify is available only during transmis-

sion for the S-BUS and I2C BUS; for other protocol

it is not defined. The SDA and SCL signal entering

the SPI are buffered in order to remove any minor

glitches. When STD bit is set to one (S-BUS or I2C

BUS selected), and TRX bit is reset (receiving da-

ta), and STOP bit is set (last byte of current com-

munication), the SPI interface does not generate

the Acknowledge, according to S-BUS/I2C BUS

specifications. PCO-SCL, PC1-SDA and PC3-

SEN lines are standard drive I/O port pins with

open-drain output configuration (maximum voltage

that can be applied to these pins is VDD+ 0.3V).

ST6380 数据表(PDF) 43 Page - STMicroelectronics

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