ST6380 datasheet(53/82 Pages) STMICROELECTRONICS

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Vertical Start Address Register (VSAR)

Address: 38h - Page 5

—

Read/Write

D7. This bit is not used

FR. FRinge background.This bit changes the

background from a box background to a fringe

background. The background is enabled by word

as defined by either BG0 or BG1.

“0” The background is defined to be a box which

is 15 x 18 dots (the 14x18 dots frame of the

character + one dot column placed left of the

character frame).

“1” The background is defined to be a fringe. The

fringe background is complete around the dis-

played character provided that it is inside the

15x18 dots frame.

Note: For the smallest character size (14TDOT,

18H) the fringe function may be either a full

fringe or a shadow background (see also

FF_SH bit of the VSR1 register).

VSA5-VSA0. Vertical Start Address. These bits

determine the start position of the first line in

the vertical direction. The 6 bits can specify 63

display start positions of interval 4H. The first

start position will be the fourth line of the dis-

play. The vertical start address is defined

VSA0 by the following formula.

Vertical Start Address = 4H(25 (VSA5) + 24

(VSA4) +23 (VSA3) + 22 (VSA2) + 21 (VSA1) + 20

(VSA0))

Note: The case of all Vertical Start Address bits

being zero is illegal.

Horizontal Start Address Register (HSAR)

Address: 39h - Page 5

—

Read/Write

D7. This bit is not used.

SBD. Space Background Disable. This bit controls

whether or not the background is displayed on

space characters. If two background colours are

used on adjacent words, then the background

should not be displayed on spaces in order to

make a nice break between colours. If an even

background around an area of text is desired, as in

a menu, then the background should be displayed

when on space characters.

“0” The background during spaces is controlled

by the background enable bits (BG0 and BG1)

located in the Background Control register.

“1” The background is not displayed when spaces

are displayed.

HSA5, HSA0 - Horizontal Start Address bits.

These bits determine the start position of the first

character in the horizontal direction. The 6 bits can

specify 64 display start positions of interval 2/fOSC

or 400ns. The first start position will be at 7.2

µs

because of the time needed to access RAM and

ROM before the first character can be displayed.

The horizontal start address is defined by the fol-

lowing formula.

Horizontal Start Address = 2/f

OSC(18 + 2

5 (HSA5)

+24 (HSA4) + 23 (HSA3) + 22 (HSA2) + 21 (HSA1)

+ 20 (HSA0))

Note: The case of all Horizontal Start Address bits

being zero is illegal.

Vertical Space Register 0 (VSR0)

Address: 3Ah - Page 5

—

Read/Write

D7. This bit is not used

SCB. Screen Blanking. This bit allows the entire

screen to be blanked.

“0” The blanking output signal BLANK is active

only when displaying characters.

“1” The blanking output signal BLANK is always

active. Characters in the display RAM are still

displayed.

When this bit is set to one, the screen is blanked

also without setting the Global Enable bit to one

(OSD disabled).

VS5, VS0. Vertical Space. These bits determine

the spacing between lines if the Vertical Space En-

able bit (VSE) in the format character is set and

the Vertical Space Select bit (VSS) is reset. If VSE

is zero there will be no spaces between lines. The

Vertical Space bits can specify one of 63 spacing

values from 4H to 252H. The space between lines

is defined by the following formula.

Space between lines = 4H(25 (VS5) + 24 (VS4) +

23 (VS3) + 22 (VS2) + 21 (VS1) + 20 (VS0))

Note: The case of all Vertical Space bits being

zero is not legal.

VSA5

VSA4

VSA3

VSA2

VSA1

VSA0

SBD

HSA5

HSA4

HSA3

HSA2

HSA1

HSA0

SCB

VS5

VS4

VS3

VS2

VS1

VS0

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