TNETX3150 datasheet(37/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

decoding the destination address (DA) and source address (SA) from the DRAM bus (continued)

The node addresses are transmitted on the DRAM bus in the Ethernet native data format. This is the same

format in which the address appears in the frame. Ethernet first transmits the least-significant bit of a data byte

on the wire. This makes the specific/group bit appear in bit 40 (least-significant bit of most-significant byte). For

example, a destination address of 0x12.34.56.78.9A. BC and a source address of 0xDE.F1.23.45.67.89 is seen

on the DD terminals as follows:

CYCLE

BIT

CYCLE

0x78

0x56

0x34

0x12

0xF1

0xDE

0xBC

0x9A

0x89

0x67

0x45

0x23

CRC checking and valid frames

The TNETX15AE determines the status of the frame when the EOB, followed by an EOF, is detected. CRC

checking is determined from the frame-status field. The code for a good CRC is frame status = 000b. All other

frame-status codings indicate that the TNETX3150/TNETX3150A/TNETX3100 aborts the frame due to either

a CRC error, a FIFO overflow, or a network error. The frame status is checked only when the option of adding

addresses to TNETX15AE tables on a good CRC is indicated rather than immediately adding a new address.

If a good CRC is required to add an address, the ADD state machine simply waits from source address time

to CRC time. It can be interrupted by a lookup for another port, but no ADD/DEL or other lower-priority activity

on any other port can take place. This might cause TNETX15AE to miss adding addresses when expected.

operating logic arbitration

The lookup table is contained in the external SRAM. All of the TNETX15AE logic operations share access to

this SRAM. An arbitration scheme is implemented to give all logic operations access to the SRAM while meeting

the lookup timing requirements.

The TNETX15AE contains seven logic operations that require the use of the SRAM bus. They are the RAM

initialization logic operation (INIT), the lookup logic operation (LKUP), the delete logic operation (DEL), the add

logic operation (ADD), the management address-lookup logic operation (FIND), the RAM registers RAMaddr

and RAMdata (REG), and the aging logic operation (AGE).

The arbiter assigns a priority to each logic operation. The highest priority is assigned to the INIT logic operation

to initialize the TNETX15AE after a reset. After initialization, LKUP becomes the logic operation with the highest

priority because it is the logic operation that is the most time critical. The next priority level is shared by ADD

and DEL. Register-based accesses (REG) are followed by the FIND logic operation. AGE becomes the lowest

priority. Figure 4 shows the priorities of the TNETX15AE logic operations.

The arbiter grants the bus to the logic operation with the highest priority that is currently requesting the bus. Each

logic operation requests the bus by asserting its request signal. The arbiter assigns the bus to that logic

operation by asserting its grant signal. If no logic operation is requesting the bus, the arbiter grants the bus to

AGE for background aging operations.

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