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TNETX3150 数据表(PDF) 71 Page - Texas Instruments |
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TNETX3150 数据表(HTML) 71 Page - Texas Instruments |
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71 / 78 page ![]() TNETX15AE ADDRESS-LOOKUP DEVICE SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997 71 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating conditions OSCIN clock MIN NOM MAX UNIT tc(OSCIN)† Cycle time, OSCIN 20 ns tw(OSCINH) Pulse duration, OSCIN high 8 10 ns tw(OSCINL) Pulse duration, OSCIN low 8 10 ns Frequency drift† ±50 ppm † TNETX15AE is designed to use the OSCIN input from the companion TNETX3150/TNETX3150A/TNETX3100 to be able to snoop on the TNETX3150/TNETX3150A/TNETX3100-DRAM bus. The accuracy and drift are constrained by TNETX3150/TNETX3150A/TNETX3100 use of OSCIN for Ethernet state machines. timing requirements over recommended operating conditions (see Figure 24) power-on reset NO. MIN MAX UNIT 1 td(OSCIN) Delay time, from VCC↑ to RESET↑ 25 ms 2 td(RESET) Delay time, from OSCIN ↑ to RESET↑ 25 ms 3 td(AUTO) Delay time, from RESET ↑ to EEPROM autoload over 50 ms OSCIN (Input) VCC(5V) (Input) VCC (Input) 1 2 RESET (Input) Normal Operation Signals‡ Valid ‡ A pullup or active logic is required for each input to have known logic levels at all times, especially during reset when an I/O output is disabled. 3 Figure 24. Power-On Reset Timing |
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