TNETX3150 datasheet(49/78 Pages) TI

49 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

internal registers

The internal registers are used to initialize and/or software-reset the TNETX15AE, select the TNETX15AE

startup and routing options, check the number of nodes within the TNETX15AE and statistics, enable

management-based operations on the lookup table, and interface with the on-chip or external SRAM, the

EEPROM, and any MII-managed devices.

The internal registers are described in the detailed

internal register section of this document.

The following sections provide additional information on the use of internal registers to access the SRAM, MII

devices, and EEPROM.

lookup-table SRAM access

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO

ADDRESS

RAMsize

0x00

RAMaddr

0x20

RAMdata

0x24

The TNETX15AE SRAM can be accessed with the RAMaddr and RAMdata registers. The algorithm for reading

and writing to the RAM is similar to that for reading and writing to the internal registers; the address of the location

to access is placed in the RAMaddr register and the data is read from or written to the RAMdata register.

This interface also has an auto-increment function, which is selected from the INC bit in the RAMaddr register.

The auto-incrementer increments by one when the most-significant byte of the RAMdata register is read or

written to.

The DIO state machine must request access to SRAM via the SRAM bus scheduler. A write to SRAM is queued

when the most-significant byte of the RAMdata register is written. A read of SRAM is queued when either byte

of the RAMdata register is read through the DIO port.

serial interface – MII-managed devices

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO

ADDRESS

SIO

0x08

The TNETX15AE gives the programmer an easy way to implement a software-controlled bit-serial interface.

This interface is most appropriate in implementing an MII management serial interface.

MII devices, which implement the management interface, consisting of MDIO and MDCLK, are accessed in this

way though the SIO register. In addition (for PHYs that support this) the TNETX15AE implements a

MII-management signal, MRESET, to hardware-reset MII PHYs.

MDIO requires an external pullup for operation. The I/O direction is controlled by the MTXEN bit, and the

external terminal state is set from or read in MDATA. The complete serial interface (MDIO, MDCLK, MRESET)

can be placed in a high-Z state through the MDIOEN bit in SIO.

The TNETX15AE does not implement any timing or data structure on its serial interface. Appropriate timing and

frame format must be assured by the management software by setting or clearing bits at the right time and in

the right order. Refer to the IEEE Std 802.3u specification and the data sheet for the MII-managed device for

the nature and timing of the MII waveforms.

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