TNETX3150 datasheet(51/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

software reset

The TNETX15AE is software reset by setting the RESET bit to a 1 in the control register (0x00,0x09 DIO). The

TNETX15AE remains in the reset state until this bit is cleared. All internal registers are initialized to default

values during a software reset, except for the control register, which keeps its current value. Reading the internal

registers is allowed during a software reset, but the user cannot write to any register (except for the

control register).

The EEPROM auto-loading process does not start during a software reset. The user must assert the LOAD bit

in the control register for auto-loading to start.

EEPROM initialization/automatic loading (LOAD)

The TNETX15AE automatically loads selected registers from an attached 24C02 EEPROM after a hardware

reset or when the LOAD bit in the control register is set. Up to eight 24C02 EEPROMs can be connected across

the same serial interface. They are distinguished by separate addresses that are selectable by pulling address

terminals up or down on each EEPROM. The TNETX15AE requires the automatic loading information in device

number 0x00, starting at location 0x00.

The TNETX15AE determines if the EEPROM device is present. Several conditions cause the TNETX15AE to

determine that a device is not present. If EDIO is pulled down, the EEPROM is assumed to be not present. If

the EEPROM fails to acknowledge (ACK) on data writes, the EEPROM is not present. If the cyclic redundancy

check (CRC) in the EEPROM does not match the internally calculated CRC, the EEPROM is assumed to be

not present.

When no EEPROM is detected, The TNETX15AE sets the NEEPM bit in the control register to a 1, and the

TNETX15AE is placed in a reset state (RESET and NEEPM are set in the control register) while the registers

assume their default values.

The automatic loader reads the register values from the EEPROM and programs the TNETX15AE accordingly.

The last register written is the control register.

The automatic loader can initialize and start up the TNETX15AE if the START bit in the control register is

programmed in the EEPROM. This allows for initialization and startup without a host CPU.

During the automatic loading, no DIO operations are permitted. Both reads and writes stall, that is, SRDY does

not come true on a pending operation until the EEPROM load cycle is over. The load cycle should take (bits per

word access on the EEPROM)

× (words read) × 100 kHz, or 27 × 43 × 100 kHz, or 12 ms. To sense the end,

wait for a sample register read to complete, or wait 15 ms.

If load is followed by start, then the INITD bit in the control register can be used to indicate when all the setup

is done. The download bit, LOAD bit, RESET bit, and any other read only or reserved bits cannot be set during

automatic loading. The CRC for the EEPROM is calculated using the information written in the EEPROM

although information may not be written to the TNETX15AE. For example; a value of 0x8F or 0xFF in the

EEPROM for RAMsize is written as 0x0F in the TNETX15AE since bits 7, 6, 5, and 4 are reserved, but the

calculated CRC for the EEPROM for each case is different.

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