MFC2000 datasheet(21/426 Pages) ETC

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Multifunctional Peripheral Controller 2000

MFC2000

100723A

Conexant

3-1

3. Hardware Interface

3.1

Pin Description

Table 3-1. Pin Description (1 of 6)

Pin Name

Pin No.

I/O

Input

Type

Output

Type

Pin Description

PRTIRQn

U14

HU5VT

(Hysteresis, Pull up) Interrupt from the external

printing ASIC (active low)

AUXCLK

K20

2XT3V

Auxiliary clock output for using as the master clock

for external devices

A[11:0]/A[23:12]

A20,B20,B19,B

18,B17,C20,C1

9,C18,C17,D20,

D19,D18

I/O

5VT

3XT5VT

Address bus (12-bit), A[23:12] and A[11:0] are

muxed out through same pins.

ALE

C16

2XT5VT

Address Latch output signal for latching A[23:12]

externally

AE[2]/GPO[14]/SSTXD2/

ROM_CONFIG[0]

A19

I/O

D5VT

2XT5VT

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[14] or

TX data output for SSIF2 (ROM_CONFIG[0] input

during the reset period)

AO[2]/GPO[15]/SSSTAT2/RO

M_CONFIG[1]

A18

I/O

D5VT

2XT5VT

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[15] or

Status input for SSIF2 (ROM_CONFIG[1] input

during the reset period)

AE[3]/GPO[16]/

CLK_CONFIG[0]

A17

I/O

D5VT

2XT5VT

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[16]

(CLK_CONFIG[0] input during the reset period)

AO[3]/GPO[17]/

CLK_CONFIG[1]

D16

I/O

D5VT

2XT5VT

(Pull down) Address bit for external ROM mux in

the ROM interleave access mode or GPO[17]

(CLK_CONFIG[1] input during the reset period)

D[15:0]

A12,B12,C12,A

13,B13,C13,D1

3,A14,B14,C14,

A15,B15,C15,D

15,A16,B16

I/O

5VT

2XT5VT

Data bus (16-bit)

RDn

D12

3XT5VT

Read strobe (active low)

WREn/DOEEn

4XT5VT

Write strobe for the lower byte (active low) or

DRAM output enables selects used for non-

interleave mode and interleave modes. DOEEn is

used for reading the even address bank (active

low).

WROn/DOEOn

4XT5VT

Write strobe for the higher byte (active low) or

DRAM output enables selects used for non-

interleave mode and interleave modes. DOEOn is

used for reading the odd address bank (active

low).

ROMCSn

D10

2XT5VT

ROM chip select (active low)

CS[1]n

2XT5VT

I/O chip select (active low).

CS[0]n

G18

2XT3V

SRAM chip select (active low) (VRTC powered)

RASn[1:0]

F19,F18

2XT3V

DRAM row Address select for bank 0 and 1(active

low) (VDRAM powered)

CASOn[1:0]

E17,F20

2XT3V

DRAM column odd address selects used for non-

interleave mode and interleave mode. (VDRAM

powered)

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MFC2000 数据表(PDF) 21 Page - List of Unclassifed Manufacturers

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