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MFC2000 数据表(PDF) 26 Page - List of Unclassifed Manufacturers

部件名 MFC2000
功能描述  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

MFC2000 数据表(HTML) 26 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
3-6
Conexant
100723A
Table 3-1. Pin Description (6 of 6)
Pin Name
Pin No.
I/O
Input
Type
Output
Type
Pin Description
DMACYC/ CLK_CONFIG[2]
M18
I/O
U5VT
2XT5VT
(Pull up) DMA Cycle-the DMA logic has control of
the external bus. (CLK_CONFIG[2] input during the
reset period)
WAITn
J17
O
U5VT
2XT5VT
(Pull up) Wait (active low)-reflects the wait states
being used by the ARM processor.
CACHEHIT/
JTAG_MODE_SEL
J18
I/O
U5VT
2XT5VT
(Pull up) Cache hit-the ARM is retrieving data from
the cache memory (JTAG_MODE_SEL during the
reset period, “1” – ARM JTAG selected
SEQ
N17
O
D5VT
2XT5VT
(Pull down) Sequential Address Access. (Used
with nMREQ to indicate memory access type. Only
required if using co-processor cycles)
SSD_DIBRX
F3
O
Internal test pin. Leave it open.
TX_DATA
F2
O
Internal test pin. Leave it open.
SDAA_GPIO_INT
F1
O
Internal test pin. Leave it open.
VSS
L1,L2,L3,L4,U1
0,V10,W10,Y10,
L17,L18,L19,L2
0,A11,B11,C11,
D11
-
Digital ground (16 pins)
VDD
A10,B10,C10,K
1,K2,K3,K4,U11
,V11,W11,Y11,
K17,M20
-
+3.3V digital power (13 pins)
P80VSS
M1
-
Digital ground for P80 DSP
P80VDD
M2
-
+3.3V digital power for P80 DSP
VGG1
M17
-
+5V Power for the +5V tolerant pads
VGG2
D14
-
+5V Power for the +5V tolerant pads
VGG3
D5
-
+5V Power for the +5V tolerant pads
VGG4
M4
-
+5V Power for the +5V tolerant pads
VDRAM
E18
-
Battery Power for DRAM refresh.
VRTC
F17
-
Battery Power for RTC
(NC)
A3,B3,A4,B4,C4
,D4,A5,B5,C5,A
6,B6,C6,D6,A7,
B7,C7,D7,D8
-
18 RESERVED pins



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